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A64E06161
Preliminary
Document Title 1M X 16 Bit Low Voltage Super RAM Revision History
Rev. No.
0.0 0.1
1M X 16 Bit Low Voltage Super RAM
History
Initial issue Change VCC range and VCCQ range Change page access time from 20ns to 25ns Change operation current (ICC1) from 25mA to 15mA(-70) Change operation current (ICC1) from 20mA to 12mA(-85) Change standby current (ISB1) from 80uA to 100uA Delete reduce memory size 16M, partial array refresh 16M Change operation current (ICC2) form 5mA to 3mA(-70, -85) Change PAR current 12Mb=90uA, 8Mb=80uA, 4Mb=70uA Change TCR current +85C=100uA +70C=90uA Change TCR current +45C=85uA +15C=75uA
Issue Date
October 12, 2003 November 30, 2004
Remark
Preliminary
PRELIMINARY
(November, 2004, Version 0.1)
AMIC Technology, Corp.
A64E06161
Preliminary
Features
Operating voltage: VCC: 1.7V to 1.95V VCCQ: 1.7V to VCC Access times: tAA = 70ns (max.) Page Access times: tPAA = 25ns (max) Current: A64E06161 series: Operating Current (Icc1) : 15mA (max.) Standby Current (Isb1) : 100uA (max) Deep Power Down Standby Current (IZZ) : 10A (max.) 4-word page length Support 4 distinct operation modes for reducing standby power : Deep Power Down (DPD) mode Reduce Memory Size (RMS) mode (4M, 8M, 12M) Partial Array Refresh (PAR) mode (4M,8M,12M) Temperature Compensated Refresh (TCR) mode Industrial operating temperature range: -25C to +85C for - I Available in 48-ball Mini BGA (6X8) package.
1M X 16 Bit Low Voltage Super RAM
General Description
The A64E06161 is a low operating current 16,777,216-bit super RAM organized as 1,048,576 word by 16bit and operated on low power supply voltage from 1.7V to 1.95V. It is built using AMIC's high performance CMOS DRAM process. Using hidden refresh technique, the A64E06161 provides a compatible asynchronous interface and data can be read in 4-word page mode for fast access times. The A64E06161 has an internal register named the Configuration Register (CR) that controls the operation. The A64E06161 is designed for reducing current consumption during hidden self refresh and operating through following mode: Deep Power Down (DPD) mode, Reduce Memory Size (RMS) mode, Partial Array Refresh (PAR) mode and Temperature Compensated refresh (TCR) mode. This A64E06161 is suited for low power application such as mobile phone and PDA or other battery-operated handheld device.
Pin Configuration
Mini BGA (6X8) Top View 1 A 2 3 4 5 6
LB I/O8
OE
A0 A3
A1 A4
A2
ZZ
I/O0 I/O2 VCC VSS I/O6 I/O7 NC
B
HB
I/O10 I/O11 I/O12 I/O13 A19 A8
CE I/O1 I/O3 I/O4 I/O5 WE A11
C D E F G H
I/O9 VSSQ VCCQ I/O14 I/O15 A18
A5 A17 NC A14 A12 A9
A6 A7 A16 A15 A13 A10
A64E06161G
PRELIMINARY
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AMIC Technology, Corp.
A64E06161
Block Diagram
VCC
A0
16,777,216 MEMORY ARRAY
VSS
DECODER
VCCQ
A18 A19
VSSQ
I/O0
INPUT DATA CIRCUIT
COLUMN I/O
I/O8
INPUT DATA CIRCUIT
I/O7
I/O15
CE ZZ LB HB OE WE
CONTROL CIRCUIT
Pin Description
Symbol Description
A0 - A19
Address Inputs Chip Enable Input Sleep Enable Input (When ZZ is low, the CR register can be loaded or the device can enter DPD mode or PAR mode). Data Input/Outputs Write Enable Input Byte Enable Input (I/O0 to I/O7) Byte Enable Input (I/O8 to I/O15) Output Enable Input Power Ground Provide isolated power to I/O for improved noise immunity Provide isolated / Ground to I/O for improved noise immunity No Connection or VSSQ
CE
ZZ
I/O0 - I/O15 WE LB HB OE VCC VSS VCCQ VSSQ NC
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A64E06161
Recommended DC Operating Conditions (TA = 0C to + 70C or -25C to 85C)
Symbol Parameter Min. Max. Unit
VCC VSS VCCQ VSSQ VIH VIL CL
Supply Voltage Ground Supply Voltage I/O only Ground I/O only Input High Voltage Input Low Voltage Output Load
1.7 0 1.7 0 1.4 -0.2 -
1.95 0 VCC 0 VCCQ + 0.2 +0.4 30
V V V V V V pF
Absolute Maximum Ratings*
VCC to VSS . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V VCCQ to VSSQ . . . . . . . . . . . . . . . -0.3V to VCCQ+0.3V IN, IN/OUT Volt to GND . . . . . . . . -0.3V to VCCQ + 0.3V Storage Temperature, Tstg . . . . . . . . -55C to +125C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W Soldering Temp. & Time . . . . . . . . . . . . 260C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol Parameter
(TA = 0C to + 70C or -25C to 85C, VCC = 1.7V to 1.95V, VCCQ = 1.7V to VCC GND = 0V)
-70 Min. Max. Min.
-85 Max.
Unit
Conditions
ILI
Input Leakage Current
-
1 1
-
1 1
A
VIN = GND to VCCQ
ILO
Output Leakage Current
A
CE = VIH or ZZ = VIL or OE = VIH or WE = VIL VI/O = GND to VCCQ
Min. Cycle, Duty = 100% VIH CE = VIL, ZZ = VIH = VCCQ, VIL = 0V, II/O = 0mA
ICC1 Dynamic Operating Current ICC2
-
15
-
12
mA
-
3
-
3
mA
CE = VIL, ZZ = VIH = VCCQ, VIL = 0V, f = 1MHz, II/O = 0mA CE VCCQ - 0.2V ZZ VCCQ - 0.2V VIN 0V
IOL = 0.2 mA IOH = -0.2mA
VIH
ISB1 VOL VOH
Standby Power Supply Current Output Low Voltage Output High Voltage
VCCQ-0.2
100 0.2 -
VCCQ-0.2
100 0.2 -
A
V V
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A64E06161
Deep Power Down Specifications and Conditions
Symbol IZZ Description Conditions Typ. Max. Units A
Deep Power-Down
VIN = VCCQ or 0V; +25C ZZ = LOW CR[4] = 0
10
Partial Array Refresh Specifications Conditions
Symbol Description Conditions Density Array Partition Typ. Max. Units A A A
IPAR
Partial Array Refresh Current
VIN = VCCQ or 0V ZZ = LOW CR[4] = 1
12Mb 8Mb 4Mb
3/4 1/2 1/4
90 80 70
Note: IPAR (MAX) values measured with TCR set to 85C
Temperature Compensated Refresh Specifications Conditions
Symbol Description Conditions Density Max Case Temperatures Typ. Max. Units A A A A
ITCR
Temperature Compensated Refresh Standby Current
VIN = VCCQ or 0V Chip Disabled
16Mb
+85C +70C +45C +15C
100 90 80 70
Note: 1. ITCR (MAX) values measured with FULL ARRAY refresh. 2. This device assumes a standby mode if the chip is disabled ( CE HIGH).
Truth Table
CE
ZZ
H L L L H
OE
WE
LB
HB
I/O0 to I/O7 Mode
I/O8 to I/O15 Mode
VCC Current
H H H L L
X X X X L
X X X L H
X X X X L L H L
X X X X L H L L H L X
Not selected Not selected Not selected Not selected Read Read High - Z Write Write Not Write/Hi - Z High - Z
Not selected Not selected Not selected Not selected Read High - Z Read Write Not Write/Hi - Z Write High - Z
ISB1 IZZ*2 IPAR*2 Load CR Register ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2
L L
H H
X H
L H
L H X
Note: 1. X = H or L 2. DPD is enable when CR register A4 is "0"; otherwise, PAR is enable
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A64E06161
Capacitance (TA = 25C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* CI/O*
Input Capacitance Input/Output Capacitance
-
6 6
pF pF
VIN = 0V VI/O = 0V
* These parameters are sampled and not 100% tested.
Initialization
The A64E06161 is initialized in the power-on sequence according to the following. 1. To stabilize internal circuits, after turning on the power, a 200s or longer wait time must precede any signal toggling. 2. After the wait time, it can be normal operation.
Power on Chart
VCC(min) VCC CE ZZ
200us Wait Time
Normal Operation
Notes: 1. Following power application, make CE high level during the wait time 200us interval. 2. After power on sequence, the normal operating ZZ must keep at high.
Standby Mode State Machines
Power On CE = VIH Wait 200us Initial State CE = VIL, ZZ = VIH HB or/and LB = VIL Active Mode CE = VIL ZZ = VIH CE = VIH, ZZ = VIL CE = VIL ZZ = VIH CE = VIH, ZZ = VIH
CE = VIH ZZ = VIH
CE = VIH ZZ = VIL
Standny Mode
CE = VIH, ZZ = VIH CE = VIH, ZZ = VIL CE = VIH, ZZ = VIL
PAR Mode (12M/8M/4M bits)
DPD Mode (Data Invalid)
Note: DPD is enable when CR register A4 is "0"; otherwise, PAR is enable.
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A64E06161
Configuration Register
The configuration register (CR) defines how the A64E06161 operates and whether page mode read accesses are permitted. The register is automatically loaded with default setting during power on and can be updated anytime while the device is operating in a normal state.
CR Register Description
Reserved PAGE TCR
ZZ Enable Deep Sleep Array On/Off on ZZ
PAR Top/Bottom Selection
PAR Memory Selection
A19 - A8
Bit(s)
A7
A6
A5
Name
A4
A3
A2
Deserved
A1
A0
A19 - A8 7 6, 5
Reserved Page Mode on/off Temperature Compensated Register Section
Reserved, All must be set to "0" 0 - Page Mode Disabled (Default) 1 - Page Mode Enabled 11 - +85C (Default) 00 - +70C 01 - +45C 10 - +15C 0 - DPD Mode Enabled 1 - DPD Mode Disabled (Default)
0 - PAR Mode (Default) 1 - RMS Mode 0 - Bottom (Default) 1 - Top 01 - 3/4 Array (12M) 10 - 1/2 Array (8M) 11 - 1/4 Array (4M)
4
3 2 1-0
ZZ Enable Deep Sleep Array On/Off on ZZ PAR Top/Bottom Half Selection PAR Memory Selection
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A64E06161
CR Register Update - Timing Waveform
tWC
Address CE
Eight Lower-order address bits (A7-A0) Define PAR Register
tCW tZZCE tAW tAS tWR tWP
WE ZZ
tZZWE
tZZMIN
Figure 1: CR register update-Timing waveform
Notes: 1. VIH(MAX) = VCCQ + 0.2V for pulse durations less than 20ns. 2. VIL(MIN) = -1V for pulse duration less than 20ns. 3. Overshoot and undershoot specifications are characterized and are not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.) and TA = 25C. 5. The timing values for the CR Register Update are shown in the "Partial Array Mode Timing" table and "AC Characteristics" table.
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A64E06161
Page Mode Description
The Page Mode operation takes advantage of the fact that adjacent address can be read in shorter period of time than random addresses. Write operations do not support comparable page mode functionality. The Page Mode operation can be enabled and disabled in the CR register. If the CR register bit A7 is set to a "1", Page Mode operation is enabled. The A64E06161 provides following operation mode for reducing power: 1. Deep Power Down (DPD) mode 2. Reduce Memory Size (RMS) mode 3. Partial Array Refresh (PAR) mode 4. Temperature Compensated Refresh (TCR) mode to a " 0". The device stays in the Deep Power Down (DPD) mode until ZZ is driven High. If the A4 register bit is set equal to "1", Deep Power Down (DPD) mode will not be activated. Once the A64E06161 exits the Deep Power Down (DPD) mode, the content of the CR register is destroyed and the CR register would go into the default state upon normal operation.
2. Reduce Memory Size (RMS) mode
In this mode, the A64E06161 can be operated as a reduced size device. For example, one can operate the 16M A64E06161 as a 4M or 8M memory block. Reduce Memory Size (RMS) mode can be enabled by having the appropriate setting in the CR register. The mode is effective once ZZ goes high and remains in the Reduce Memory Size (RMS) mode until full array restored by setting the CR register again. At power on, all four section of the device are activated and the A64E06161 enter into its default state of full memory size and refresh space.
1. Deep Power Down (DPD) mode
In this mode, the internal refresh is turned off and all data integrity of the array is lost. Deep Power Down (DPD) mode is entered by ZZ low and keep 10us with A4 register bit set
Variable Address Space - Address Patterns
A2 0 0 0
1 1 1 0 0 0 1 1 1
A1, A0 Refresh Section 11 One-fourth of the Die 10 Half of the Die 01 Three-fourths of the Die
11 10 01 11 10 01 11 10 01 One-fourth of the Die Half of the Die Three-fourths of the Die
Partial Array Refresh Mode (A3 =0, A4 = 1) Address 00000h - 3FFFFh (A19 = A18 = 0) 00000h - 7FFFFh (A19 = 0)
00000h - BFFFFh (A19 : A18 11) C0000h - FFFFh (A19 = A18 = 1) 80000h - FFFFFh (A19 = 1)
Size 256K x 16 512K x 16 768K x 16
256K x 16 512K x 16 768K x 16 256K x 16 512K x 16 768K x 16 256K x 16 512K x 16 768K x 16
Density 4M 8M 12M
4M 8M 12M 4M 8M 12M 4M 8M 12M
40000h - FFFFFh (A19: A18 00) Reduced Memory Size Mode (A3 = 1, A4 = 1) One-fourth of the Die 00000h - 3FFFFh (A19 = A18 = 0) Half of the Die 00000h - 7FFFFh (A19 = 0) Three-fourths of the Die 00000h - BFFFFh (A19 : A18 11) One-fourth of the Die Half of the Die Three-fourths of the Die C0000h - FFFFh (A19 = A18 = 1) 80000h - FFFFFh (A19 = 1) 40000h - FFFFFh (A19 : A18 00)
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A64E06161
Memory Block Spilt
Bottom Address Range
0 1 0 0 1 0 1
1/2 Address Space Refresh Active Address Space: A0-A18 A<19> = <0>
1
1/4 Address Space Refresh Active Address Space: A0-A17 A<18,19> = <0,0>
0
1 0
0
1 0 1
1
3/4 Address Space Refresh Active Address Space: A0-A19 A<18,19> = <0,0>,<1,0>,<0,1> Full Address Space Refresh Active Address Space: A0-A19 A<18,19> =
Top Address Range
0 1 0 0 1 0 1
1/2 Address Space Refresh Active Address Space: A0-A18 A<19> = <1>
1
1/4 Address Space Refresh Active Address Space: A0-A17 A<18,19> = <1,1>
0
1 0
0
1 0 1
1
3/4 Address Space Refresh Active Address Space: A0-A19 A<18,19> = <1,0>,<0,1>,<1,1> Full Address Space Refresh Active Address Space: A0-A19 A<18,19> =
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3. Partial Array Refresh (PAR) mode
In this mode, customers can turn off section of A64E06161 in stand-by mode to save standby current. The A64E06161 is divided into four 4M sections allowing certain section to be active. The array partition to be refreshed is determined by the respective bit in the CR register. When ZZ is active low, only the portion of the array that is set in the CR register is refreshed and the data is keep at a certain section of memory. The Partial Array Refresh (PAR) mode is only available during standby time ( ZZ low). Once ZZ is turned high, the A64E06161 goes back to operating in full array refresh. For Partial Array Refresh (PAR) mode to be activated, the register bit, A4 must be set to a "1" value. To change the address space of the Partial Array Refresh (PAR) mode, the CR register must be updated using the CR register description. If the CR register is not updated after power on, the A64E06161 will be in its default state and the whole memory array will be refreshed.
Partial Array Refresh - Entry/Exit
ZZ
1us suspend tCDR
Partial Array Mode/ Deep Power Down Mode
tR
CE or UB / LB
Figure 2: Partial Array refresh - Entry/Exit
Partial Array Mode Timings
Parameter tZZWE
tCDR tR tZZMIN tZZCE tZZBE
Description
ZZ LOW to WE LOW Chip Deselect to ZZ LOW Operation Recovery Time (Deep Power Down Mode only) Deep Power Down Mode Time ZZ LOW to CE LOW ZZ LOW to UB / LD LOW
Min.
0
Max. 1
Unit s
s
200 10 0 0 1 1
s s s s
Notes: 1. OE and the data pins are in a "don't care" state while the device is in Partial Array Mode. 2. All other timing parameters are as shown in the switching characteristics section. 3. tR applies only in the Deep Power Down Mode.
4. Temperature Compensated Refresh (TCR) mode
In this mode, the hidden refresh rate can be optimized for the operating temperature. At higher temperature, the DRAM cell must be refreshed more often than at lower temperature. By setting the temperature of operation in CR register, the refresh rate can be optimized to meet the low standby current at given operating temperature. There are four selections (+15C, +45C, +70C, +85C) in the CR register description.
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Avoid Timing
Following Figure 3 is show you an abnormal timing which is not supported on Super RAM.
CE
WE
Less than 30ns
Address
Note: Address = A0 ~ A19 Under CR register A7 = 0 Address = A2 ~ A19 Under CR register A7 = 1
Figure 3
Operation When Page Mode is Enabled
The maximum CE pulse width should not exceed 10s to accommodate orderly scheduling of refresh (Figure 4).
CE
tCEM 10us
Note: Timing constraints when page mode is enabled.
Figure 4: Timing constraint for tCEM
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AC Characteristics
Symbol
Read Cycle tRC tSKEW tAA tACE tBE tOE tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH tASC tAHC tCEH tPC tPAA tNPPC Write Cycle tWC tSKEW tCW tBW tAS tAW tWP tWR tWHZ tDW tDH tOW tASC tAHC tCEH tWEH tCEM
(TA = 0C to + 70C or -25C to 85C, VCC = 1.7V to 1.95V, VCCQ = 1.7V to VCC GND = 0V)
Parameter Min.
Read Cycle Time Address Skew Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Byte Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Byte Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change Address Setup to CE Low Address Hold Time from CE High CE High Pulse With Page Read Cycle Time Page access Time Normal to Page Read Cycle Time Write Cycle Time Address Skew Chip Enable to End of Write Byte Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write Address Setup to CE Low Address Hold Time from CE High CE High Pulse With WE High Pulse With Maximum CE Pulse width 70 5 5 5 0 0 0 10 0 0 10 25 70 70 60 0 70 50 0 30 0 5 0 0 10 10 -
-70 Max.
10000 10 70 70 35 35 14 14 14 25 10 10000 10 14 10
-85 Min.
85 5 5 5 0 0 0 10 0 0 10 25 85 85 70 0 85 60 0 35 0 5 0 0 10 10 -
Unit Max.
10000 10 85 85 45 45 14 14 14 25 10 10000 10 14 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
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Timing Waveforms
Read Cycle 1(1, 2, 4, 6)
tSKEW tRC tSKEW tRC
Address
tAA
tOH
tAA
tOH
DOUT
tASC
CE
Read Cycle 2-1(1, 3, 6)
tSKEW
tRC
tRC
tSKEW
Address
tASC tAA tCEH tAHC tASC tAA tAHC
CE
tACE tCLZ5 tCHZ5 tACE tCLZ5 tBE tCHZ5
HB , LB
tBE
tBLZ5
tBHZ5
tBLZ5
tBHZ5
OE
tOE tOLZ5 tOHZ5 tOE tOLZ5 tOHZ5
DOUT
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A64E06161
Read Cycle 2-2(1, 3, 6)
tSKEW tRC
tSKEW
tRC
tSKEW
Address
tASC tAHC
tAA
tAA
CE
tACE tCLZ5 tCHZ5
HB , LB
tBE
tBE
tBLZ5
tBHZ5
tBLZ5
tBHZ5
OE
tOE tOLZ5 tOHZ5 tOE tOLZ5 tOHZ5
DOUT
Notes:
1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested. 6. ZZ is high for Read Cycle.
Timing Waveforms
Words Page Read Cycle Timing Chart
tNPPC tRC tSKEW tPC tPC tPC tSKEW
Address A2~A19 Page Address (A0~A1)
tASC
AN
AN+1
AN+2
AN+3
tAHC tCHZ tACE tPAA tOH tPAA tOH tPAA tOH tOH
CE
I/O (Output) OE, HB, LB
tOE tBE
QN
QN+1
QN+2
QN+3
tOHZ tBHZ
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Timing Waveforms (continued)
Write Cycle 1-1(6) (Write Enable Controlled)
tSKEW tWC tWC tSKEW
Address
tASC tAW tCW tCEH tAHC tASC tAW tCW tAHC
CE
tBW tBW
HB , LB
tAS1 tWP2 tWR3 tAS1 tWP2 tWR3
WE
tDW tDH tDW tDH
Data In
tWHZ4 tOW tWHZ4 tOW
Data Out
Write Cycle 1-2(6) (Write Enable Controlled)
tSKEW tWC tSKEW tWC tSKEW
Address
tASC tAHC
CE
tBW tBW
HB , LB
tAS1 tWP2 tWR3 tWEH tDW tDH tDW tDH tAS1 tWP2 tWR3
WE
Data In
tWHZ4 tOW tWHZ4 tOW
Data Out
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Timing Waveforms (continued)
Write Cycle 2-1(6) (Chip Enable Controlled)
tSKEW tWC tWC tSKEW
Address
tAW tASC tCW2 tAHC tASC tCEH tCW2 tAW tAHC
CE
tBW tWR3 tBW tWR3
HB , LB
tWP tWP
WE
tDW tDH tDW tDH
Data In
tWHZ4 tOW tWHZ4 tOW
Data Out
Timing Waveforms
Write Cycle 3-1(6) (Byte Enable Controlled)
tSKEW tWC tWC tSKEW
Address
tAW tASC tCW tAHC tASC tCEH tCW tAW tAHC
CE
tAS1 tBW2 tWR3 tAS1 tBW2 tWR3
HB , LB
tWP tWP
WE
tDW tDH tDW tDH
Data In
tWHZ4 tOW tWHZ4 tOW
Data Out
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Write Cycle 3-2(6) (Byte Enable Controlled)
tSKEW tWC tSKEW tWC tSKEW
Address
tASC tAW tAHC
CE
tAS1 tBW2 tWR3 tAS1 tBW2 tWR3
HB , LB
tWP tWP
WE
tDW tDH tDW tDH
Data In
tWHZ4 tOW tWHZ4 tOW
Data Out
Notes: 1. 2. 3. 4. 5. 6.
tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ). tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle. OE level is high or low. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested. ZZ is high for Write Cycle.
AC Test Conditions
Input Pulse Levels Input Rise And Fall Time Input and Output Timing Reference Levels Output Load VCCQ * 0.2 to VCCQ * 0.8 2 ns (10% to90%) 0.5 * VCCQ See Figures 5
VCCQ
2.7K
OUT 30pF Test Point
2.7K
Figure 5. Output Load Circuit
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Ordering Information
Operating Current Max. (mA) Deep Power Down Mode Standby Current Max. (A)
Part No.
Access Time (ns)
Package
A64E06161G-70 A64E06161G-85 A64E06161G-70I A64E06161G-85I
70 85 70 85
15 12 15 12
10 10 10 10
48B Mini BGA 48B Mini BGA 48B Mini BGA 48B Mini BGA
Note: -I is for industrial operating temperature range
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Package Information 48LD CSP (6 x 8 mm) Outline Dimensions
(48TFBGA)
TOP VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER 123456 b (48X) 654321
unit: mm
A B C D E F G H
E1
A B C D E F G H
E
B A 0.10 C 0.20(4X)
e
e D1 D
SIDE VIEW
C
SEATING PLANE A1 A
Symbol
Dimensions in mm
MIN. --0.20 5.90 7.90 ------0.30
NOM. --0.25 6.00 8.00 3.75 5.25 0.75 0.35
MAX. 1.20 0.30 6.10 8.10 ------0.40
A A1 D E D1 E1 e b
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS 0.3mm (NSMD)
PRELIMINARY
(November, 2004, Version 0.1)
19
AMIC Technology, Corp.

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